Hexadecimal Codes
The display module data bus accepts 8-bit wide instruction codes which are directed to the instruction register when RS =0 (low) and R/W =0 (low).  When writing programs, the equivalent hexadecimal code is easier to use than the 8-bit wide instruction codes.  Key operational codes are listed below in hexadecimal format.
Command
Description
Instruction
Code
(Hex)
RS
Code
R/W
Code
Display Control
On
0C 0 0
Blank (All Memory
Retained)
0A,08 0 0
Clear Display
& Home Cursor
01 0 0
Home Cursor 02 0 0
Cursor
On 0E 0 0
OFF 0C 0 0
Wink 0D 0 0
Shift Left 10 0 0
Shift Right 14 0 0
Home 02 0 0 
Command
Description?
Instruction
Code
(Hex)
RS
Code
R/W
Code
Cursor Travel
Character Entry
Left 04 0 0
Right 06 0 0
Shift Display with
Data Entry
Left 07 0 0
Right 05 0 0
Shift Display with-
out Data Entry
Left 18 0 0
Right 1C 0 0
Display Data Addresses
Home Position
1st Line
80 0 0
Home Position
2nd Line
C0 0 0

Instruction Code Definitions Outline
Two registers of the HD44780, the Instruction Register (IR) and the Data Register (DR) only can be controlled by MPU directly.  Control information is temporarily stored in these registers, prior to internal operation start, to allow interface to various types of MPUs which operate in different speeds from HD44780 internal operation or to allow interface to peripheral control ICs. The HD44780 internal operation is determined by signals sent from MPU. These signals include register selection signals (RS), read/write signals (R/W) and data bus signals (DB0 – DB7) are called instructions in the paragraph. Table above shows the instructions and the execution time of the instructions. Details are explained in the following sections. The instructions can be divided into the following 4 types: (1)  Instructions that designate the HD44780 functions such as display format, data length, etc.
(2)  Instructions that give internal RAM addresses.
(3)  Instructions that perform data transfer with internal RAM.
(4)  Other instructions.

In the normal use, instructions of category (3), which sends display data, is used most frequently. However, since the HD44780 internal RAM addresses are configured to be automatically incremented (or decremented ) by + 1 after each data write, MPU program load is lessened. Specifically, display shift is performed concurrently with display data write, and this enables the user to develop systems with minimum time and maximum efficiency of programming. When an instruction is being executed (during internal operation), the busy flag DB7 is active high. This must be monitored when high speed operation is planned (=50KHz).

 

Clear Display
RS R/W DB7 DB0
Code 0 0 0 0 0 0 0 0 0 1
Writes character code “20″ (hexadecimal) into all the DD RAM addresses. the cursor returns to Address 0 (Add=’80′) and display, if it has been shifted, returns to the original position. In other words, display disappears and the cursor goes to the left edge of the display (the first line if 2 lines are displayed).
Return Home
RS R/W DB7 DB0
Code 0 0 0 0 0 0 0 0 1 *
* Don’t Care
Returns the cursor to Address 0 (ADD=’80′) and display, if it has been shifted, to the original position. The DD RAM contents remain unchanged.
Entry Mode Set
RS R/W DB7 DB0
Code 0 0 0 0 0 0 0 0 I/D 0
I/D: Increments (I/D= 1) or decrements (I/D=0) the DD RAM address by one upon writing into or reading from the DD RAM a character code. The cursor moves to the right when incremented by one. The same applies to writing and reading of CG RAM.
S: Shifts the entire display to either the right or the left when S is 1; to the left when I/D=1 and to the right when I/D=0. Therefore, the cursor looks as if it stood still with the display only moved. Display is not shifted when reading from the DD RAM. Display is not shifted when S=0.
Display ON/OFF Control
RS R/W DB7 DB0
Code 0 0 0 0 0 0 1 D C B
D:
Display is turned ON when 0=1 and OFF when D=0. When display is turned off due to D=0, the display data remains in the DD RAM and it can be displayed immediately by setting D=1.
C: The cursor is displayed when C=1 and not displayed when C=0. Even if the cursor disappears, function of I/D, etc. does not change during display data write. The cursor is displayed using 5 dots in the 8th line when the 5×7 dot character font is selected and the 11th line when 5×10 dot character font is selected.
B: The character residing at the cursor position blinks when B=1. The blink is done by switching between all the black dots and display characters at 0.4 second interval. The cursor and the blink can be set concurrently.

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5 x 7 Dot
Character
Font
5 x 10 Dot
Character
Font
(a) Cursor Display
Example
(b) Blink Display
Example
Cursor or Display Shift 
RS R/W DB7 DB0
Code 0 0 0 0 0 0 S/C R/L * *
*Don’t Care
Shifts the cursor position or display to the right and the left without writing or reading the display data. This function is used for correction or search of display.
S/C R/L
0 0 Shifts the cursor position to the left. (AC is decremented by one.)
0 1 Shifts the cursor position to the right. (AC is incremented by one.)
1 0 Shifts the entire display to the left. The cursor follows the display shift.
1 1 Shifts the entire display to the right. The cursor follows the display shift.
Function Set
RS R/W DB7 DB0
Code 0 0 0 0 0 DL N F * *
* Don’t Care
DL: Sets interface data length. Data is sent or received in 8-bit length (DB7-DB0) when DL=0, 1 and 4-bit length (DB7-DB4) when DL=0. When 4-bit length is selected, data must be sent or received twice.
N: Sets number of display lines.
F: Sets Character Font.
N F No. of
Display Lines
Character
Font
Duty
Cycle
0 0 1 5 X 7 dots 1/8
0 1 1 5 X 10 dots 1/11
1 * 2 5 x 7 dots 1/16

*Cannot display 2 lines with 5X10 dot character font.

Set CG RAM Address
RS R/W DB7 DB0
Code 0 0 0 1 A A A A A A
<= Higher Order Bits Lower Order Bits =>
Sets the CG RAM address in a binary number of AAAAAA to the address counter, and data is written or read from the MPU related to the CG RAM after this.
Set DD RAM Address
RS R/W DB7 DB0
Code 0 0 1 An A A A A A A
<= Higher Order Bits Lower Order Bits =>
Sets the DD RAM address in a binary number of AnAAAAAA to the address counter and data is written or read from the MPU related to the DD RAM after this. However, when N=0 (1-line display,) AnAAAAAA is “80″ to “CF” (hexadecimal). When N=1 (2-line display), AnAAAAAA is “80″ to “A7″ (hexadecimal) for the first line, and “C0″ to “E7″ (hexadecimal) for the second line.
Read Busy Flag and Address
RS R/W DB7 DB0
Code 0 1 BF A A A A A A A
<= Higher Order Bits Lower Order Bits =>
Reads Busy Flag (BF) that indicates the system is internally operating on an instruction received before. When BF=1, it indicates that internal operation is going on and the next instructions not accepted until BF is set to “0″. Check the BF status before the next write operation and at the same time, the value of the address counter expressed in a binary number of AAAAAA. The address counter is used by both the CG and DD RAM address, and its value is determined by the previous instruction. Address contents are those of the CG RAM or DD RAM previously shown.
Write Data to CG or DD RAM
RS R/W DB7 DB0
Code 1 0 D D D D D D D D
<= Higher Order Bits Lower Order Bits =>
Writes binary 8-bit data DDDDDDDD to the CG or the DD RAM. Whether the CG or the DD RAM is to be written is determined by the previous designation (CG RAM address setting or DD RAM address setting). After write, the address is automatically incremented or decremented by one according to entry mode. Display shift also follows the entry mode.
Read Data from CG or DD RAM
RS R/W DB7 DB0
Code 1 1 D D D D D D D D
<= Higher Order Bits Lower Order Bits =>
Reads binary 8-bit data DDDDDDDD from the CG or the DD RAM. Whether the CG RAM or the DD RAM is to be read is determined by the previous designation. Prior to entering this read instruction, either the CG RAM address set instruction or the DD RAM address set instruction must be executed. If it is not done, the first read data becomes invalid, and data of the next address is read normally from the second read. After read, the address is automatically incremented or decremented by one according to the entry mode. However, display shift is not performed regardless of entry mode types.